Dec 15 12:44 PM PDT

ESD Design Considerations for Mobile Device Applications

Typical 8KV ESD pulse simulated by ESD generator

Figure 1. Typical 8KV ESD pulse simulated by ESD generator. (Click image to enlarge)

In the 1970’s, rubbing your feet across the green shag carpet to generate a static charge in order to torture your siblings was fun and would do no damage to the low-tech, large, and robust electronic components of the time. Today, portable devices designed for the increasingly busy, yet very well connected, mobile user has led to the integration of more and more inputs and outputs on our favorite gadgets. Higher current densities, smaller silicon, and limited space available for chip protection all tend to increase the sensitivity of electronic components to transient electrical overstress events such as ESD (electrostatic discharge). Reducing the impact of these transients helps prevent data corruption when devices are talking to each other and improves overall reliability.

Figure 1 shows a typical ESD characteristic curve. To simulate a real world contact discharge event, an ESD generator applies an ESD pulse to the device under test. Characteristics of this test are the short rise time and the short pulse duration of less than 100ns, indicating a low-energy, static pulse. Voltage levels generated by these sources can be extremely high since their charge is not readily distributed over their surfaces or conducted to other objects. While briefly painful, these high voltages are not dangerous to humans because the pulse duration is very short, and therefore the energy present is very low. However, their effect on sensitive electronic components can be very destructive.

Chip scale ESD devices help protect sensitive circuitry from ESD damage.

Figure 2. Chip scale ESD devices help protect sensitive circuitry from ESD damage. (Click image to enlarge)

The increasing usage of laptop computers, smart phones, and other mobile equipment makes it more likely that users will touch I/O connector pins during the connecting and disconnecting of cables. Under normal operating conditions, touching an exposed port or interface can result in voltage discharges in excess of 30 kV.

Small-geometry semiconductor devices can be damaged due to excessive voltage, high current levels, or a combination of both. High voltage levels can cause gate oxide punch-through, while excessive current can cause junction failures and metallization traces to melt.

Most electronic devices must meet a minimum of 8 kV contact discharge or 15 kV air discharge, based on the international standard IEC61000-4-2. Some silicon devices have built-in protection that is rated up to 2 kV and some have no protection built-in. So in order to enhance their survivability, additional off-chip protection circuits must be designed into the system.

There are two main design considerations in ESD protection design for high-speed I/O interfaces.

1. ESD protection circuits for high-speed I/O interfaces must be robust enough to effectively protect the thin gate oxide in the internal circuits against ESD stress.

2. The degradation of high-speed circuit performance due to the parasitic effects of ESD protection devices needs to be minimized. If the ESD protection device has high capacitance, it can attenuate the signal and cause data loss. At very high frequencies that reach well into the GHz range there may be few components that have a low enough capacitance (less than a picofarad) to prevent signal distortion.
The continuing trend toward discrete component miniaturization often presents designers with difficult and time-consuming engineering prototyping and rework challenges as well as manufacturing process control issues. New, smaller chip-scale ESD devices (down to 0201 sizes) meet the performance requirements for high-speed applications and can also help mitigate assembly and manufacturing challenges.
As shown in Figure 2, chip-scale ESD devices are used to divert a potentially damaging charge away from sensitive circuitry and protect the system from failure. Combining the advantages of an active silicon device with a traditional Surface-Mount Technology (SMT) passive packaging configuration, they are easier to install and rework than traditional semiconductor-packaged ESD devices.

Even when you are not deliberately trying to torture your siblings, electrostatic damage to electronic devices can occur at any time, from the factory floor to the end-user’s home. ESD transients may disrupt equipment operation or result in potential damage. Small form factor, low capacitance chip-scale ESD devices offer a simple, cost-effective solution to these challenges.

More on Circuit Protection
TE Circuit Protection offers a variety of Polymer and Silicon ESD protection devices. For more information on our devices you can visit our document library or our website.

This article was originally published on the Power Systems Design online Experts Exchange.

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